A novel pipelined carry adder design based on half adder

<span lang="EN-US">A new design of binary parallel adder circuit is presented in this paper. The pipeline technique applied to implement a group half (HA) blocks architect the proposed adder. pipelined carry (PCA) method suitable for carrying out desired by using HA circuits XOR and AND gates. reduces critical path delay 27% compared with ripple (RCA) relatively lowers logic gates 55% look-ahead (CLA). coded implemented simulated on Cyclone IV FPGA kit platform. Results show that needs 7.69 ƞ Sec time provide output values. suggested PCA more attractive than conventional future electronic applications. </span>